Self-aligned silicide (salicide) technology is required in modem integrated circuit and semiconductor device fabrication to lower the resistance of polysilicon gates, sources and drains to reduce RC delay, i.e., the gate speed performance index wherein less delay produces increased gate speed performance. On example of a well known silicide technology is cobalt silicide (CoSi2). CoSi2 process are commonly used for sub quarter micron and beyond technology. Unfortunately, the agglomeration effect of CoSi2 on very narrow line polysilicon gates that are less than 65 nanometers, often limits its extendibility to the fabrication of shorter gates.
Nickel silicide (NiSi) technology appears to be emerging as a dominant solution to very narrow line polysilicon gates because it provides better sheet resistance (Rs) for narrow line polysilicon gates, less junction leakage, less silicon (Si) consumption, and can even improve the drive current (Idsat) of an NFET or PFET.
With respect to the NiSi, there are still some concerns about monosilicide phase stability, film thermal stability, and plasma damage resistance of NiSi while implementing this process.
Accordingly, a method or process is needed which allows NiSi to be implemented successfully in very narrow line polysilicon gate technology.